1. Field of the Invention
The present invention relates to SCSI bus interface circuits and in particular relates to a circuit for generation of variable period and variable width REQ or ACK signal pulses as used in synchronous SCSI bus transfers.
2. Description of Related Art
Small Computer System Interface (SCSI) buses are common interconnect buses between computer systems and peripheral devices such as mass storage devices. The SCSI bus is a parallel bus comprising a number of parallel data signal paths (collectively referred to as the data bus) and a plurality of control signal paths to coordinate the exchange of information over the bus. A device wishing to initiate communications with another device is referred to as an initiator and the other device is referred to as the target.
The REQ and ACK control signals of the SCSI bus are used to pace the rate of transfer of information over the data bus. The target applies a signal to the REQ signal path to assert that it is ready for the next data transfer. The initiator applies a signal to the ACK signal path to assert that the transfer has completed. This sequence continues for each unit of data transferred until the transfer is completed (or interrupted for other reasons).
Generally, SCSI buses operate in one of two data transfer modes: asynchronous transfers and synchronous transfers. In the asynchronous transfer mode, each unit of data transferred requires a complete cycle of the REQ and ACK signals. Specifically, for each transfer, the REQ signal is asserted by the target, followed by assertion of the ACK signal by the initiator (indicating that the transfer is complete), followed by de-assertion of the REQ signal, lastly followed by de-assertion of the ACK signal. This asynchronous mode of data transfer is limited, in part, by the minimum timing requirements for the assertion and de-assertion of the REQ and ACK signals. Other timing constraints of asynchronous transfer mode further limit the maximum bandwidth available.
In read operation of the synchronous transfer mode, a number of data transfers may be completed by REQ signals from the target before a first ACK signal is required from the initiator. The number of such transfers permitted before an ACK signal is required is a configurable parameter referred to as the REQ/ACK offset. In a write operation, one or more REQ signal assertions precede the data and ACK signal. So long as the differences between the number of REQ signals asserted and the number of ACK signals asserted is less than the REQ/ACK offset parameter value, the transfer may continue (until exhaustion or interruption). This counting mechanism for pacing of transfers enables faster transfer. Bursts of data are thereby transferred without awaiting the handshake signal for each unit of transfer.
Parameters may be programmed in each SCSI device to define the REQ/ACK offset as well as other parameters used in the REQ/ACK handshake protocol for synchronous transfer mode. Specifically, a SCSI SDTR command is used to "negotiate" the REQ/ACK offset value as well as a transfer period. The transfer period is the minimum time allowed between leading edges of successive REQ pulses and of successive ACK pulses to meet the device requirements for successful reception of data.
Programmable parameters define the pulse timing of the REQ or ACK signal pulses. The assertion period is the minimum time that a target shall assert REQ while using synchronous data transfers (or the assert time for ACK with respect to an initiator device). The total pulse cycle period (transfer period) is also specified to fully characterize the pulse timing. The de-assertion period of the signal may be derived from the transfer and the assertion period.
This collection of programmable parameters permit flexible definition of the period and assertion shape (timing) of the REQ and ACK pulses used in SCSI synchronous transfer mode. By supporting shorter transfer period times and shorter pulse width timings, the synchronous data transfer rate can be increased dramatically as is known in the art. Specifically, it is presently known to achieve transfer rates as high as 40 MB per second on an 8-bit wide SCSI bus operating in synchronous transfer mode.
SCSI interface circuits in devices therefore include circuits for programming the waveform timing and period of REQ and ACK pulses for application to the SCSI bus signal paths. SCSI interface circuits (typically VLSI integrated circuits--ICs) typically include a section whose function is to flexibly control the timing and period of the REQ and ACK pulses. The generation of REQs and ACKs is complicated in that each device type (target or initiator) may be different and therefore capable of differing signal speeds. A REQ/ACK generator design must therefore account for the various combinations of functions and states.
Prior REQ/ACK generation circuits may have utilized complex finite state machine models and/or a plurality of counter circuits in their designs to achieve this flexible programmability. Such prior solutions are relatively complex. It is always a problem in IC designs to minimize complexity by reducing the number of lower level circuits (gates) required for a particular function. Simplicity in the design, as measured by reduced gate count, typically translate to a number of important benefits including: smaller chip/wafer size, lower power consumption, reduced gate delays (higher speeds), and others.
It is apparent from the above discussion that a need exists for a simpler REQ/ACK pulse signal generator for integration into SCSI interface peripheral control integrated circuits.